The present invention relates generally to the bonding of input/output electrical connection pins to a chip carrying substrate in an electronic system. More particularly, the present invention relates to surface mount bonding of input/output pins to pads on an organic substrate.
Microprocessors and many other complex electrical components basically consist of a package that houses an integrated circuit (IC). The package, which acts as an electrical bridge between the IC and a printed circuit board, includes a substrate and an internal metallurgy system that routes power, ground, and signals between the printed circuit board and an IC attached to the substrate.
A package is typically connected to a printed circuit board using either a set of input/output pins (e.g., a xe2x80x9cpin grid arrayxe2x80x9d) or solder balls (e.g., a xe2x80x9cball grid arrayxe2x80x9d). In a pin grid array package, an array of input/output pins are connected to the bottom surface of the package. During assembly of a printed circuit board, the pin grid array is mated to a complimentary socket on the printed circuit board. One advantage to using pin grid array packages is that the package can later be removed from the printed circuit board and replaced.
Two technologies for manufacturing pin grid array packages are commonly used in the semiconductor manufacturing industry. These technologies are surface mount technology and wirebond technology. Surface mount technology involves attaching pins to pads on the bottom surface of a ceramic substrate, thus forming electrical connections with the internal package routing system.
FIG. 1 illustrates a cross-sectional view of a ceramic, pin grid array integrated circuit package in accordance with the prior art. A ceramic substrate 102 houses an integrated circuit 104 on the substrate""s top surface. Attached to pin pads 106 on the bottom surface are surface mount pins 108. During manufacture of the package, the surface mount pins 108 are brazed to the substrate 102 with an alloy (e.g., Copper Zinc). Generally, this brazing process occurs at extremely high temperatures, which can be on the order of approximately 1000 degrees Celsius.
Because of the high temperatures necessary to braze the pins onto the substrate, surface mount pin technology is used in ceramic packages only. It has not been practical to use on organic packages, because an organic package would be damaged if heated to the temperature necessary to braze the pins to the substrate.
Even though pins could be soldered to pads on the bottom of an organic package using a tin-lead (Snxe2x80x94Pb) solder composition, such a solution is not practical. This is because, during the component manufacturing process, it is necessary to reheat the package after the pins are attached. For example, it may be necessary to connect the IC to the package or to repair and/or rework modules that are defective or defectively joined. If the pins were merely soldered to pads on the package, the subsequent re-heating would cause the pin solder to soften or melt. This would likely result in some or all pins tilting or falling off the package.
Because organic packages cannot be heated to extremely high temperatures without becoming damaged, and because it is impractical to surface mount pins using commonly-used Snxe2x80x94Pb solder, wirebond technology is generally used to create organic packages with pin grid arrays.
FIG. 2 illustrates a cross-sectional view of an organic, pin grid array integrated circuit package in accordance with the prior art. The pin grid array package includes an organic substrate 202, embedded pins 204, and embedded traces 206. An IC 208 is housed in a cavity 210 on the upper surface of the substrate 202. All signal, ground, and power leads are brought to pads on the edge of the IC 208, and then gold wires 212 are used to connect these input/output pads to wirebond pads on the top surface of the substrate 202. These wirebond pads are electrically connected to embedded pins 204 via embedded traces 206. Because pins 204 are inserted into the substrate 202, they must be located around the perimeter of the substrate 202. This is necessary because the depth to which the pins 204 must be inserted into the substrate 202 precludes the pins from being located underneath the IC 208. FIG. 3 illustrates a bottom view of a pin configuration for the integrated circuit package illustrated in FIG. 2. Numerous pins 204 are shown to be inserted into the substrate 202 around its entire perimeter.
It is apparent from FIGS. 2 and 3 that one disadvantage to wirebond packages is that the package must be substantially larger than the IC that it houses, since the package must accommodate the peripheral, inserted pin grid array. In order to reduce the size of organic packages, xe2x80x9cflip-chipxe2x80x9d ball grid array packages are now commonly used. A xe2x80x9cflip-chipxe2x80x9d is a chip in which power, ground, and signal leads are brought to pads anywhere on the top surface of the chip. Snxe2x80x94Pb solder bumps are then printed onto the pads, and the chip is turned upside down, and aligned with pads on the top surface of the package. When the assembly is heated to the melting point of the solder, the bumps flow together.
On the bottom of the package, a ball grid array is provided in order to attach the package to the printed circuit board. The ball grid array consists of solder balls that are attached to pads on the bottom of the package. These pads are then aligned with matching pads on the printed circuit board, and the board is heated, causing the solder to melt and form contacts between the package pads and the board pads.
FIG. 4 illustrates a side view of a flip-chip ball grid array package in accordance with the prior art. The package includes an organic substrate 402 having an array of solder balls 404 attached to the bottom surface of the substrate 402. An IC 406 is attached to the top surface of the substrate 402 by solder bumps 408.
Flip-chip ball grid array packages can be substantially smaller than the wirebond packages. However, one disadvantage to ball grid array packages is that they cannot be easily removed from a printed circuit board once they have been attached. Instead, if the integrated circuit becomes damaged or the consumer wishes to changed the component, the entire circuit board must be replaced.
For the reasons stated above, there is a need in the art for an organic, integrated circuit package having surface mount pins with connections that will withstand subsequent reheating steps during assembly. Further needed is a composition that can be used to attach those surface mount pins to input/output pads on the organic package. In addition, what is needed is a process for forming strong, stable bonds between surface mount pins and pads on an organic substrate.
A method for attaching a surface mount pin to a pin pad on a bottom surface of a substrate first applies solder material to the pin pad. The solder material has a composition that includes at least Sn and Sb. The surface mount pin is then placed in contact with the solder material, and the solder material is heated to its melting temperature.
An integrated circuit package has a substrate with an internal metallurgy system that electrically connects bonding pads on a top surface of the substrate to pin pads on a bottom surface of the substrate. A plurality of input/output pins are surface mounted to the pin pads using a solder material having a composition that includes at least Sn and Sb. The solder material is disposed between bonding surfaces of each of the input/output pins, thereby bonding the input/output pins to the pin pads. An integrated circuit is located on the top surface of the substrate. The integrated circuit contains a circuit which is electrically connected to the bonding pads.
A computer system positioned on a printed circuit board has a bus, a memory coupled to the bus, and an integrated circuit package coupled to the bus. The integrated circuit package has a substrate with an internal metallurgy system that electrically connects bonding pads on a top surface of the substrate to pin pads on a bottom surface of the substrate. A plurality of input/output pins are surface mounted to the pin pads with a solder material having a composition that includes at least Sn and Sb. The solder material is disposed between bonding surfaces of each of the input/output pins, thereby bonding the input/output pins to the pin pads. A microprocessor is located on the top surface of the substrate. The microprocessor contains a circuit which is electrically connected to the bonding pads.